1. Field of the Invention
The present invention relates to a printed circuit board and, more particularly, to a method for fabricating a circuit pattern of a printed circuit board that is capable of easily forming a fine pitch circuit pattern and improving a reliability.
2. Description of the Background Art
FIGS. 1A to 1J are sequential process of a method for fabricating a circuit pattern of a printed circuit board in accordance with a conventional art.
The process of fabricating a circuit pattern of a printed circuit board in accordance with a conventional art will now be described with reference to FIGS. 1A to 1J.
First, as shown in FIG. 1A, a base material 10 is prepared. The base material 10 is formed by coating a copper foil 16 at both sides of an insulation material 12 with a predetermined thickness.
With reference to FIG. 1B, a plurality of through holes 18 are formed in the base material 10. The through holes 18 serve as a path for electrically connecting the copper foil coated at both sides of the insulation material 12, and as such it can be formed with various sizes and as many as desired according to a circuit design.
And then, as shown in FIG. 1C, after the through holes 18 are formed, a copper plated layer 20 is formed at a surface of the base material 10. That is, the copper plated layer 20 is formed also at the inner surface of the through holes 18 as well as at the surface of the copper foil 16, electrically connecting the copper foil 16 formed at both sides of the insulation material 12.
And, as shown in FIGS. 1D and 1E, an etching resist 22 is coated at the surface of the copper plated layer 20, which is then exposed. The exposing process is performed such that an exposing mask 26 with a plurality of openings 24 is positioned at both surfaces of the base material 10 with the etching resist 22 coated thereon, on which ultraviolet ray is irradiated, so that the ultraviolet ray is partially irradiated at the etching resist 22 through the openings 24 formed at the exposing mask 26.
When the exposing process is completed, as shown in FIG. 1F, a development process proceeds to remove the etching resist 22 of the exposed portion. That is, the etching resist at the portion to which ultraviolet ray has been irradiated is removed to expose the copper plated layer 20, while the etching resist 22 without ultraviolet irradiated thereto as being covered by the exposed mask 26 remains, not exposing the copper plated layer 20.
After the development process is completed, as shown in FIG. 1G, an etching process proceeds to remove the exposed copper plated layer 20 and the copper foil 16.
And then, as shown in FIG. 1H, the remaining etching resist 22 is removed. Then, the copper plated layer 20 remaining at both surfaces of the insulation 12 by being protected by the etching resist 22 and the copper foil 16 form a circuit patterns 28.
As the etching resist 22 is removed, as shown in FIG. 1I, a resin is plugged in the through hole 18 and regions between the circuit patterns 28 to form a resin layer 30. And then, a photoresist 34 is coated at a surface of the resin layer 30. At this time, some of the circuit patterns 28 are used as a connection pad 32 for electrical connection with outside and the photoresist 34 is not coated at the circuit pattern used as the connection pad 32.
That is, circuit patterns 28 are formed by the copper foil 16 and the copper plated layer 20 at both surfaces of the insulation material 12, and electrically connected to each other by the copper plated layer 20 coated at the inner surface of the through holes 18.
And then, as shown in FIG. 1J, a gold-plated layer 36 is formed on the portion of the connection pad 32 for connection to other electronic parts. The gold-plated layer 36 serves to ensure a firm attachment when a gold wire is connected to the connection pad 32 or a solder ball is formed on the connection pad 32.
FIG. 2 is a partial perspective view of the printed circuit board in accordance with the conventional art, and FIG. 3 is a sectional view showing the connection pad 32 with the gold plated layer 36 formed thereon in accordance with the conventional art.
To sum up, the printed circuit board in accordance with the conventional art has a structure that the circuit patterns 28 are formed at the surface of the insulation layer 12, on which the photoresist 34 is coated, and the gold plated layer 36 is formed at the connection pad 32, where no photoresist 34 is coated, for connecting with other electronic parts.
A printed circuit board such as a flip chip package or a chip scale package (CSP) having almost the same size as the semiconductor chip is in demand increasingly, and the connection pad is in the tendency of sharply increase in number as the semiconductor chip is of high density. Accordingly, in order to form more circuit patterns in the same area for a signal transmission with the semiconductor chip, the width and the thickness of the circuit pattern is reduced and a space between circuit patterns becomes fine.
However, the circuit pattern fabrication method of a printed circuit board in accordance with the conventional art has the following problems.
That is, first, because the circuit pattern 28 or the connection pad 32 is formed through the etching process, its bottom portion attached at the insulation layer 12 is relatively wide and becomes narrow as it goes to the upper portion, causing a problem that it is difficult to attach the gold wire or the solder ball.
In other words, in the etching process, an etching solution permeates from the upper portion of the connection pad 32 to its lower portion, so that the upper portion of the connection pad is more removed than the lower portion as the upper portion is exposed by the etching solution longer time than the lower portion, leaving a trapezoid shape. Thus, there is a limitation to form a fine circuit pattern 28 or a connection pad 32 in terms of thickness and width.
Second, because the circuit pattern 28 and the connection pad 32 are first formed and then the resin layer 30 or the solder resist is coated, the surface flatness is degraded due to the existence of the protruded circuit pattern 28 and the connection pad 32, resulting in a high possibility that the solder resist 30 may be cracked due to a thermal impact, and when a semiconductor chip is molded at the printed circuit board, a flow of the molding compound is not good.
Third, as shown in FIG. 3, the upper surface and the left and right surfaces of the connection pad 32 are exposed on which the copper plated layer 20 and the gold-plated layer 36 are formed. The gold-plated region is relatively enlarged and the gold-plated layer 36 is formed long in the downward direction of both sides of the connection pad 32, causing much problem for insulation between the adjacent connection pads. In addition, the thickness of the copper plated layer 20 and the gold plated layer 36 formed at the side makes it difficult to obtain a fine pitch.